JPH0311036B2 - - Google Patents

Info

Publication number
JPH0311036B2
JPH0311036B2 JP58144252A JP14425283A JPH0311036B2 JP H0311036 B2 JPH0311036 B2 JP H0311036B2 JP 58144252 A JP58144252 A JP 58144252A JP 14425283 A JP14425283 A JP 14425283A JP H0311036 B2 JPH0311036 B2 JP H0311036B2
Authority
JP
Japan
Prior art keywords
flip
shift register
clock signal
transfer clock
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58144252A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6035400A (ja
Inventor
Setsushi Kamuro
Takaaki Hirano
Mikiro Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP58144252A priority Critical patent/JPS6035400A/ja
Priority to US06/633,989 priority patent/US4630295A/en
Publication of JPS6035400A publication Critical patent/JPS6035400A/ja
Publication of JPH0311036B2 publication Critical patent/JPH0311036B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers

Landscapes

  • Shift Register Type Memory (AREA)
  • Dc Digital Transmission (AREA)
JP58144252A 1983-08-05 1983-08-05 相補形金属酸化膜半導体を用いた送信装置 Granted JPS6035400A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP58144252A JPS6035400A (ja) 1983-08-05 1983-08-05 相補形金属酸化膜半導体を用いた送信装置
US06/633,989 US4630295A (en) 1983-08-05 1984-07-24 Low power consumption CMOS shift register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58144252A JPS6035400A (ja) 1983-08-05 1983-08-05 相補形金属酸化膜半導体を用いた送信装置

Publications (2)

Publication Number Publication Date
JPS6035400A JPS6035400A (ja) 1985-02-23
JPH0311036B2 true JPH0311036B2 (en]) 1991-02-15

Family

ID=15357770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58144252A Granted JPS6035400A (ja) 1983-08-05 1983-08-05 相補形金属酸化膜半導体を用いた送信装置

Country Status (2)

Country Link
US (1) US4630295A (en])
JP (1) JPS6035400A (en])

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4692641A (en) * 1986-02-13 1987-09-08 Burr-Brown Corporation Level shifting circuitry for serial-to-parallel converter
GB2187578B (en) * 1986-03-08 1989-11-15 Int Computers Ltd Parallel to serial converter
JPS63194422A (ja) * 1987-02-09 1988-08-11 Fujitsu Ltd パラレル−シリアル変換回路
US4982414A (en) * 1987-12-21 1991-01-01 Ricoh Company, Ltd. Abbreviated incrementer circuit
JPH0313122A (ja) * 1989-06-12 1991-01-22 Mitsubishi Electric Corp 分周回路
US5230014A (en) * 1991-06-17 1993-07-20 Honeywell Inc. Self-counting shift register
JPH0528289A (ja) * 1991-07-24 1993-02-05 Nec Corp レジスタ制御回路
US5473755A (en) * 1992-06-01 1995-12-05 Intel Corporation System for controlling data stream by changing fall through FIFO last cell state of first component whenever data read out of second component last latch
ES2078173B1 (es) * 1993-12-30 1998-01-16 Alcatel Standard Electrica Arquitectura de circuitos integrados digitales.
JPH11145789A (ja) * 1997-07-29 1999-05-28 Sharp Corp 低消費電力化レジスタ回路
JP4497708B2 (ja) * 2000-12-08 2010-07-07 三菱電機株式会社 半導体装置
JP4682485B2 (ja) * 2001-09-06 2011-05-11 株式会社デンソー メモリ制御装置及びシリアルメモリ
US7127667B2 (en) * 2002-04-15 2006-10-24 Mediatek Inc. ACS circuit and viterbi decoder with the circuit
TW530464B (en) * 2002-05-07 2003-05-01 Mediatek Inc Survive path memory circuit and Viterbi decoder with the circuit
JP4051682B2 (ja) * 2003-08-06 2008-02-27 ソニー株式会社 クロック制御回路と集積回路
JP2005159737A (ja) * 2003-11-26 2005-06-16 Oki Electric Ind Co Ltd 可変分周回路
TWI255622B (en) * 2004-10-21 2006-05-21 Mediatek Inc Method of computing path metrics in a high-speed Viterbi detector and related apparatus thereof
JP4894376B2 (ja) * 2006-06-29 2012-03-14 富士通セミコンダクター株式会社 半導体集積回路装置
JP5089367B2 (ja) * 2007-12-18 2012-12-05 古河電気工業株式会社 パルス発生装置
CN101861625B (zh) * 2007-12-27 2014-04-16 夏普株式会社 移位寄存器
US7667494B2 (en) * 2008-03-31 2010-02-23 Lsi Corporation Methods and apparatus for fast unbalanced pipeline architecture

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3258696A (en) * 1962-10-01 1966-06-28 Multiple bistable element shift register
JPS4514086Y1 (en]) * 1969-11-13 1970-06-15
US3614632A (en) * 1970-10-14 1971-10-19 Lawrence M Lelbowitz Digital pulse width generator
US3753124A (en) * 1972-08-16 1973-08-14 Parke Davis & Co Manual set system for shift register
US4334194A (en) * 1978-12-26 1982-06-08 The United States Of America As Represented By The Secretary Of The Army Pulse train generator of predetermined pulse rate using feedback shift register
JPS624960Y2 (en]) * 1979-09-13 1987-02-04
JPS57158095A (en) * 1981-03-25 1982-09-29 Seiko Instr & Electronics Ltd Shift register circuit
US4472821A (en) * 1982-05-03 1984-09-18 General Electric Company Dynamic shift register utilizing CMOS dual gate transistors

Also Published As

Publication number Publication date
JPS6035400A (ja) 1985-02-23
US4630295A (en) 1986-12-16

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